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TX IF/BBA WITH AGC
S1M8657
INTRODUCTION
48-LQFP-0707
S1M8656A/8657 are CDMA/AMPS Dual Mode IF/ baseband IC which is divided into three main parts - IF frequency processing, baseband processing , and digital interface. The receiver IC (S1M8656A) and transmitter IC (S1M8657) are provided as a KIT. S1M8656A is a receiver IC, installed with a Rx AGC, Baseband Converter, Baseband analog filter, and A-D Converter. It can send a digital baseband signal to the digital baseband IC. The S1M8657 is a transmission-only IC, installed with a Tx AGC, IF frequency converter, analog filter, D-A Converter, PLL, 8-bit A-D Converter for the system monitor, and 3-input analog switch. It connects the digital baseband IC to the RF processing. Designed to operate in direction connection with the MSM, S1M8656A and S1M8657 are fabricated on the Samsung's 0.5um high-speed, high-frequency BICMOS processing and can achieve superior high frequency and low power digital operations. Its operating voltage is 2.7V - 3.6V, and operating temperature -30C - +85C.
48-BCC-7.0 x7.0
FEATURES
* * * * * * * * * CDMA/AMPS Dual Mode AGC output signal range : 90dB Built-in QPSK baseband to IF converter Built-in Tx I and Q LPF Built in I,Q 8-BIT DAC Built-in programmable Tx IF PLL Built-in VCO for QPSK converter and IF conversion Built-in 8-BIT GP ADC with 3-input analog switching Built-in 3-line Serial Port Interface (SPI)
ORDERING INFORMATION
Device + S1M8657X01-E0T0 + S1M8657X01-F0T0 +: New product Package 48-LQFP-0707 48-BCC-7.0x7.0 Operating Temperature -30 to +85C -30 to +85C
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S1M8657
TX IF/BBA WITH AGC
BLOCK DIAGRAM
TX_VCO_T1 TX_VCO_T2
PDISET
GPENA
PDOUT
TX-PLL Synthesizer
GPCLK
GPIN1
GPIN2
GPIN3
TCXO
LOCK
ADC 8 LPF DAC
GPDATA
x TX_IF1 TX_IF2 TAGC_CONT + 1/2 DIV. 90D-PSN x 3-line Serial Port Interface Mode control SMSB/CLK FMB/DATA SLSB/PAON IDLEB/STB FM_MOD SEN
TXD0-7 TCLK
8 TCLKB LPF LPF DAC
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S1M8657
PIN CONFIGURATION
TXVCO_T2
TXVCO_T1
FM_MOD
48
47
46
45
44
43
42
41
40
39
38
TX_IF1 TX_IF2 GND TAGC_CONT GND VCC GND N.C VCC
37
PDISET
PDOUT
GND
GND
GND
VCC
VCC
VCC
N.C
1 2 3 4 5 6 7 8 9
36 35 34 33 32
LOCK TCXO SLSB/CLK IDLEB/STB FMB/DATA SEN SMSB/PAON GPIN3 GPIN2 GPIN1 GPCLK GPDATA
S1M8657
31 30 29 28 27 26 25
GND 10 TXD0 11 TXD1 12 TXD2 13 TXD3 14 TXD4 15 TXD5 16 TXD6 17 TXD7 18 TCLK 19 TCLKB 20 VDDM 21 GND 22 VCC 23 GPENA 24
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TX IF/BBA WITH AGC
PIN DESCRIPTION
PIN 1 2 NAME TX_IF1 TX_IF2 I/O AO Description Outputs differential signal to the IF output signal pin. Output format is an open-collector. Only operates in the CDMA/FM talk mode. An external components pull it up using VDD when operation is not allowed. DC input for AGC gain control. This input is the PDM control signal from the modem, which was converted to a digital signal in the R-C filter. This pin has high impedance when not in operation. Not used in this product. Transmit data input pins for transmit 8-bit D/A converter TXD7 is the MSB.
4
TAGC_CONT
AI
8 11 12 13 14 15 16 17 18 19 20 24
N.C TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TCLK TCLKB GPENA
DI
DI DI
Complementary inputs to transmit D/A converter. This pin is always on stand-by and is not affected by the SEN's pin conditions. If this pin changes from low to high when the TCXO is allowed, GP-ADC starts to operate as well as GPDATA and GPCLK. GP-ADC conversion data output pin. This pin cannot be operated by the SPI but must be operated by the GPENA pin. On stand-by, the pin is at low. GP-ADC conversion data synchronization pulse output pin. This pin cannot be operated by the SPI but must be operated by the GPENA pin. On stand-by, the pin is at low. 3-analog input terminals. Only the input from one of these is input to the GP-ADC. The input is selected based on the conditions of the SMSB/PAON and SLSB/CLK terminals in the SPI restrict mode and on the register value in the SPI operating mode. On stand-by, it has high impedance. SEN is the pin for the former bit of the two bits used to select the GP input in low state. This pin executes the PAON function when SEN=1 and TXMODE_CONT[3] =1 and executes the Tx Puncture mode when this pin is at low. Select pin for the use of the SPI BUS. If this pin is at high, the SPI bus can be used; if low, the SPI bus cannot be used but an external control pin can be used.
25
GPDATA
DO
26
GPCLK
DO
27 28 29
GPIN1 GPIN2 GPIN3
AI
30
SMSB/PAON
DI
31
SEN
DI
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TX IF/BBA WITH AGC
S1M8657
PIN DESCRIPTION (Continued)
PIN 32 NAME FMB/DATA I/O BI Description When SEN = high, this pin is used as the SPI data input pin; when low, it converts to the FMB, the parallel control input. In the parallel control mode, if this pin becomes low, the IC enters FM Mode and, if high, CDMA Mode. When SEN = high, this pin is used as the SPI STB(Strobe) pin; when low, it converts to IDLEB, the parallel control input. In the parallel control mode, if this pin becomes low, the IC enters the IDLE mode, and if high, TALK mode. When SEN = high, this pin is used as the SPI CLK input pin; when low, it converts to the SLSB, the parallel control input and becomes the input pin for the latter bit of the two GP input select bit. External TCXO signal input pin, whose input DC potential is 1.5V from only the input bias when not operating. Pin determining the charge pump current in the PLL, whose operating voltage is 0.64V. The resistance between this pin and GND determines the charge-pump current, which is R/0.64. Charge pump current output pin, whose peak current is R/0.64 and 11R/0.64 in the Lock mode and Acquisition mode, respectively. When not operating, it is at high impedance. FM modulation FM Baseband output signal, which is sent only in the FM Talk mode but has high impedance at any other time. Power pin for the analog circuit. Ground pin for the analog circuit.
33
IDLEB/STB
DI
34
SLSB/CLK
DI
35 37
TCXO PDISET
AI AO
38
PDOUT
AO
41 6, 45, 47 3, 5, 7, 22, 39, 44, 48 21 9, 23, 40 10
FM_MOD VDD GND
AO
VDDM VDD_DIG GND_DIG
Pin for the digital input/output circuit connected to the modem. Digital logic power pin. Digital circuit ground pin.
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TX IF/BBA WITH AGC
ABSOLUTE MAXIMUM RATINGS Characteristic Power supply Storage temperature Operating temperature Electrostatic discharge rating Symbol VCC TSTG TOPR HBM MM Value -0.5V to 3.6V -55C to +125C -30C to +85C 1500V 200V
RECOMMENDED OPERATING CONDITIONS Characteristic Power supply Ambient operating temperature Symbol Vcc Ta Value 2.7V to 3.6V -30C to +85C
ELECTRICAL CHARACTERISTICS (VCC = 3.3V, Ta = 25C) Characteristic Current consumption Current consumption Current consumption Test Conditions CDMA idle mode FM idle mode CDMA talk mode AGC gain : Min CDMA talk mode AGC gain : Max Current consumption FM talk mode AGC gain : Min FM talk mode AGC gain : Max Logic high input Logic low input Logic high output Logic low output Digital input capacitance Digital output load capacitance TCXO input impedance TXIF_OUT, TXIF_OUT/ Attach C = 2pF
Symbol Min Typ Max Units
ICRX IFRX ICTX1 ICTX2 IFTX1 IFTX2 VIH VIL VOH VOL CDI CDOL ZTCXO
VDD-0.4 VDD-0.4 5
20 20 20 40 20 40 -
100 100 30 50 30 50 0.4 0.4 5 5 -
uA uA mA mA mA mA V V V V pF pF k
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S1M8657
ELECTRICAL CHARACTERISTICS (Continued) Characteristic Tx IF Load resistance Test Conditions TXIF_OUT, TXIF_OUT/, Differential TXIF_OUT, TXIF_OUT/, Differential TXIF_OUT, TXIF_OUT/, Differential VCO input resistance VCO input capacitance Tx AGC gain control input impedance TX VCO_T1, TX VCO_T2 TX VCO_T1, TX VCO_T2 TAGC_CONT RVCO CVCO ZAGC 1.8 30 2 80 2.2 1.5 k pF k
Symbol Min Typ Max Units
RIF
-
1
-
k
Tx IF output capacitance
CIF
-
-
2
pF
Tx IF output impedance
ZIF
30
-
-
k
7
S1M8657
TX IF/BBA WITH AGC
ELECTRICAL CHARACTERISTICS Characteristic CDMA Performance Output Center Freq. Minimum output power Maximum output power AGC control voltage range Maximum operating IF frequency Output power when full scale I and Q data are input to the DAC at minimum AGC gain Output power when full scale I and Q data are input to the DAC at maximum AGC gain Input voltage examination that responds to the control input when input 15k resistance is series-connected to the TAGC_CONT Linear control range examination that measures the gain difference between control voltages, 1.0V and 2.0V. Examines how far the gain change between control voltages 1V - 2V is from the ideal Spurious measurement between @1kHz - @630kHz that appears at the IF output when two in-band 0.5F/S signal are input to the DAC Spurious measurement between @630kHz - @1.98MHz that appears at the IF output when two in-band 0.5F/S signal are input to the DAC. Spurious measurement above @1.98Mhz that appears at the IF output when two inband 0.5F/S signal are input the DAC Examines the carrier feed through when I and Q single-tone F/S in-band CDMA spread spectrum data are input. Examines the IF harmonics in the 1.23MHz range after I and Q single tone F/S data are input. Sets the control voltage so that AGC IF outputs -83.2dBm - 0.8dBm when I and Q single tone F/S data are input. Converts the noise within @100kHz - @1.98MHz to dBc/Hz. FTR MINP MAXP 0 300 -83.2 Mhz dBm dBm Test Conditions
Symbol Min Typ Max Units
VCON
0.1
2.4
V
AGC gain slope
GSLP
33
45
53
dB/V
AGC gain slope linearity In-band spurious free dynamic range Edge-band spurious free dynamic range Out-band spurious free dynamic range Carrier feed through Spurious free dynamic range: IF harmonics SNR, Noise BAND1
GLIN
-3
-
3
dB
ISpur
35
-
-
dBc
ESpur
35
-
-
dBc
OSpur
57
-
-
dBc
CF
28
dBc
ESFDR
20
-
-
dBc
OSFDR SNR1A
9.5 104
-
-
dBc dBc/Hz
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TX IF/BBA WITH AGC
S1M8657
ELECTRICAL CHARACTERISTICS (Continued) Characteristic CDMA Performance SNR, Noise BAND2 Sets the control voltage so that AGC IF outputs -83.2dBm - 0.8dBm when I and Q single tone F/S data are input. Converts the noise within @1.98MHz - @44MHz to dBc/Hz. Examines the difference between the power in the @1.23MHz band and the noise power in the 30kHz band after IS-98 specified CDMA data is input. Examines the difference between the power in the @1.23MHz band and the noise power at 1.98MHz in the 30kHz band after IS-98 specified CDMA data is input. Examines the I and Q gain and phase error. Examines the USB suppression ratio after I and Q single-tone F/S data is input. Examines the change in IF amplitude between @1kHz - @630kHz. Examines the on-off settling time of the TX block when PAON=Low in the TALK mode. Output when full scale data is input to the DAC at minimum AGC gain. Output when full scale data is input to the DAC at maximum AGC gain. Examines the input voltage responding to the control input when 15k resistance is series-connected to TAGC_CONT. Examines the gain difference between control voltages 1.0 V and 2.0V to examine the linear control band. Examines if the gain change between control voltages 1V - 2V is not ideal. Examines the noise density between @100kHz - @44MHz when single-tone F/S data is input. This characteristic generally depends on the VCO phase noise characteristics. Examines the harmonics at the IF when single -tone F/S data is input. SNR2A 116 dBc/Hz Test Conditions
Symbol Min Typ Max Units
ACPR BAND1
ACPR1
52.1
-
-
dB/ 30kHz
ACPR BAND2
ACPR2
68.1
-
-
dB/ 30kHz
Upper-side-band Suppression Amplitude flatness Tx puncturing settling time FM Performance Minimum output power Maximum output power AGC control voltage range AGC gain slope
USB
25
-
-
dBc
AF ST
-
-
1 6
dBpp us
MINPF MAXPF VCONT
-3 0.1
-
-50 VCC0.1
dBm dBm V
GSLP
33
45
53
dB/V
AGC gain slope inearity IF SNR Noise BAND1
GLIN SNRF1
-3 110
-
3 -
dB dBc/Hz
Maximum Spurious Content: IF harmonics
ESFDR OSFDR
20 9.5
-
-
dBc dBc
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S1M8657
TX IF/BBA WITH AGC
ELECTRICAL CHARACTERISTICS (Continued) Characteristic SNR, Noise BAND1 Test Conditions Sets the control voltage so that AGC IF outputs -83.2dBm - 0.8dBm when I and Q single tone F/S data are input. Converts the noise within @100kHz - @1.98MHz to dBc/Hz. Sets the control voltage so that AGC IF outputs -83.2dBm - 0.8dBm when I and Q single tone F/S data are input. Converts the noise within @1.98MHz - @ 44MHz to dBc/Hz. Examines the difference between the power in the @1.23MHz band and the noise power in the 30kHz band after IS-98 specified CDMA data is input. Examines the difference between the power in the @1.23MHz band and the noise power at 1.98MHz in the 30kHz band after IS-98 specified CDMA data is input. Examines the I and Q gain and phase error. Examines the USB suppression ratio after I and Q single-tone F/S data is input. Symbol SNR1A Min 104 Typ Max Units dBc/Hz
SNR, Noise BAND2
SNR2A
116
-
-
dBc/Hz
ACPR BAND1
ACPR1
52.1
-
-
dB/ 30kHz
ACPR BAND2
ACPR2
68.1
-
-
dB/ 30kHz
Upper-side-band Suppression
USB
25
-
-
dBc
TCXO/VCO/PLL Performance TCXO input frequency TCXO input level Tx VCO frequency Lock mode current Acquisition mode current Reference spur Max. Acquisition mode current Acquisition to Lock mode transition range Charge pump compliance voltage Phase detector unlock threshold during FM Io=16uA RSET = 39k RSET = 39k Depend on loop bandwidth fTCXO LTCXO fTVCO LC AC RS RAC WLD 14 140 1 19.68 0.5 16 160 25 2.0 500 18 180 -70 1 MHz Vpp MHz uA uA dBc mA kHz
VCHG
0.4
-
VCC0.4 12
V
ULFM
-
-
kHz
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TX IF/BBA WITH AGC
S1M8657
TIMING DIAGRAMS
TCLK Period: 203.4ns
High time: 101.7ns Low time: 101.7ns Rising time: 3 -12ns Falling time: 3 - 12ns
TCLK
90% 10% TCLK to TCLKB Phase delay: < 1.2ns
TCLKB
Data setup to TCLK transition: 20ns
TXD[7:0]
I-DATA
Q-DATA
I-DATA
Q-DATA
I-DATA
Q-DATA
Data hold after TCLK transition: > 3ns
Figure 1. CDMA Transmit DAC Timing
TCLK Period: 8.33us High time: 4.17us TCLK Low time: 4.17us Rising time: 3 - 12ns Falling time: 3 - 12ns
90% 10% TCLK to TCLKB Phase delay: < 1.2ns
TCLKB Data setup to TCLK transition: > 20ns TXD[7:0]
Q-DATA Q-DATA Q-DATA
Data hold after TCLK transition: > 3ns
Figure 2. FM Transmit DAC Timing
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S1M8657
TX IF/BBA WITH AGC
Clock period: 2.44us High time: 1.22us
Low time: 1.22us
Rising time: 3 - 12ns 10%
Falling time: 3 - 12ns 90%
GPCLK
GPENA high to conversion end: <40us
GPENA
GPENA high to GPCLK: 17us GPDATA valid before GPCLK rising edge: 50ns - 780ns
GPDATA valid after GPCLK falling edge: 50ns
GPDATA
D7
D6
D5
D4
D3
D2
D1
D0
* All timing specifications is based on GPCLK=410Khz
Figure 3. GP-ADC Timing
Clock period: 0.6 - 10us Clock duty cycle: 35 - 65%
CLK
Clcok N STB line setup time: 50ns
Clcok N+1
Clcok N+2
STB line hold time: 50 - 200ns
STB
All data transitions happen while CLK=Low
DATA line hold time: 50 - 200ns Valid data bit (N+2)
DATA
Valid data bit (N)
Valid data bit (N+1)
N+1 Data bit set-up time: > 50ns
Figure 4. 3-Line Serial Port Interface Timing
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TX IF/BBA WITH AGC
S1M8657
Functional Description S1M8657, a functional block used in Tx signal processing, is located between the RF pre-block and modem. This product converts the digital I and Q baseband signals sent by the modem to their corresponding analog signals and moves their frequencies to the IF mid-frequency, where their output levels are controlled. Then, the differential IF signal is output. Because it has the built-in SPI bus I/F and parallel mode control, it is compatible to the existing BBA2.0. The programmable Tx PLL is used to generate the precise IF mid-frequency. Here, the VCO, which oscillates at twice the IF frequency, and QPSK modulator moves the IF frequency from the baseband. The AGC, connected to the TX IF SAW filter, amplifies or reduces the IF signal level, required by the CDMA system, at a certain point. Its gain is controlled by the DC voltage in the TAGC_CONT and its output level range is approx. 90dB. The GP-ADC possessing a switch that can select from three independent inputs is as system monitor A-D converter, which senses the battery type, remaining battery amount, and temperature. Various inputs and conditions for this converter can be set via the SPI bus. Moreover, it can use the same BBA 2.0 conditions and parallel control inputs. S1M8657 uses a 0.5um BiCMOS, equipped with high-frequency bipolar and low power standardized CMOS logic, to operate safely in the low power range, consisting of power voltage between 2.7V - 3.6V and operating temperature between -30C - +85C. CDMA Transmit Signal Path S1M8657 is a transmit circuit, installed with PLL, GP-ADC and mode change switch and serial I/F. The transmit circuit has the Tx AGC, an automatic gain controller, and baseband LPF and D-A converter as well as a VCO and mixer etc. The CDMA IF output signal is a differential signal modulated to 1.23 MHz spread-spectrum for CDMA with a normal mid-frequency at 130.38MHz. The mid-frequencies are set based on the time constants of the components involved with the external VCO and Tx PLL. Tx AGC , connected to both the IF SAW filter and matching component in the IF-RF converter output located in the RF block, amplifies or reduces the signal according to the signal size. It takes its orders from the modem chip when it sets the appropriate power level as required by the CDMA system. Gain is controlled by applying a DC voltage to the TAGC_CONT pin. The applied DC is produced when the PDM signal, generated as a control signal in the modem, passes through the R-C filter. The control band of this AGC is approx. 90dB. The QPSK modulator mixes and adds the I-Q baseband signals, output from the DAC-LPF, with the I-LO and Q-LO signals, respectively, to generate the QPSK signal, which is sent to the AGC which in turn sends the differential IF to the RF signal processing block. The LO(local oscillator) signal is generated by the internal oscillating components, externally connected tank coil, and Varactor, and the externally independent PLL device is used to generate its exact oscillation mid-frequency. FM Transmit Signal Path Because the FM modulation in the S1M8657 FM circuit differs entirely from the QPSK, the FM transmit signal path is very different. The transmit circuit includes an automatic gain controller, Tx AGC, baseband LPF, D-A converter as well as the VCO and Mixer, which are all the essential blocks as included in the CDMA. The FM signal is a 12kHz modulated signal, with normal mid-frequency of 130.38MHz. These mid-frequencies are determined by the time constants of the components involved with the external VCO and Tx PLL. Tx AGC , connected to both the IF SAW filter and matching component in the IF-RF converter output located in the RF block, amplifies or reduces the signal according to the signal size. It takes its orders from the modem chip when it sets the appropriate power level as required by the CDMA system. Gain is controlled by applying a DC voltage to the TAGC_CONT pin. The applied DC is produced when the PDM signal, generated as a control signal in the modem, passes through the R-C filter. The control band of this AGC is approx. 90dB. Only the analog Q baseband signal output by the Q- path DAC-LPF is used in FM modulation and directly connected to the external Varactor Baseband to change the LO frequency to generate the FM modulation signal. This signal is sent to the AGC, which sends the differential IF to the RF signal processing block.
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TX IF/BBA WITH AGC
Serial Port Interface(SPI) S1M8657 is equipped with the Serial I/F. All internal functions can be controlled through a common bus using an external controller. The serial I/F can be used by setting pin 31(SEN) high, the pin which permits/ not permit the SPI. If the SEN becomes low, the SPI cannot be used and the BBA must be used in the existing BBA 2.0 mode. (All the internal registers are default, which makes the register have the same characteristic as BBA 2.0) Here, the modem is the master and BBA the slave. Each pin which uses the SPI bus has the following common functions. * * The STB(STROBE) for the serial bus start signal is used to reset serial data transmission. This pin is used with the IDLEB function in manual mode and designated the IDLB/STB pin. Serial BUS DATA is used for the bidirection data input /output at serial data transmission. This pin is used with the FMB function in parallel mode and designated the FMB/DATA pin. Because it is an open drain type pin, it requires the pull-up resistance of approx. 8k. Serial BUS CLK is used to synchronize the data input/output at serial data transmission. This pin is used with the SLEEPB function in manual mode and designated the SLEEPB/CLK pin.
*
The SEN(PIN31) pins decide on whether the product will used the SPI bus or parallel control inputs; if is in low, then the pins the parallel control input functions, IDLEB, FMB, and SLEEPB, but if in high these pins execute the SPI bus functions, STB, DATA, and CLK. The maximum data transmission (Clock frequency) is 1.53MHz. This product does not require any external time constants in the internal register because it can use the internal reset function. Fig. 5 shows the serial connection.
VDD 8k SLOT STB/IDLEB S1M8656A CLK/SLEEPB DATA/FMB SEN SLEEPB SBST/ADC_ENA SBCK/ADC_CLK SBDT/ADC_DATA PAON MODEM
S1M8657
SMSB/PAON STB/IDLEB CLK/SLSB DATA/FMB SEN
Figure 5. Serial Bus connection
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S1M8657
Serial Port Interface Operation The modem , the master, controls slaves such as S1M8657 using the SPI bus. The STB falling edge indicates the start of the serial I/F data transmission. The STB becomes high to mark the end of the data transmission. (Data sent after the STB turns high are not valid.) Serial line data is captured and stored as soon as the BBA or the MODEM places the clock on the falling edge. The SPI 3-line must remain high for at least 1-clock cycle in order to sent new data. The MSB always outputs the data line data. After 9-clocks, which is required to send data, the data line driver opens the data line, at which time the data line becomes high because of the external pull-up resistance. Serial Data Transfer Format S1M8656A and S1M8657 are all slave devices with the SPI bus. What differentiate them from one another is their different device IDs. Each company has its own characteristic SPI bus configuration , but normally the 3-line bus is most often used and sometimes the 2-line bus such as the IIC bus. Figure 6. shows the serial data transfer format.
STB CLK DATA Start bit
Master drive Slave Address mode=01 Dummy
0 1 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Master drive Register Address Dummy
Slave Drive Data Dummy 0 = Master write
Master drive Register Address Dummy
Master Drive Data Dummy
End bit
1= Master read
Figure 6. Serial Data Transfer Format (1) The first 2-BITs are for transmission only and this product must send '01'.(Others are not permitted.) (2) The following 6-bit data specifies the slave device, which is connected to the SPI bus and has its own ID. (3) The following 1-bit is a dummy bit, which marks the end of the 8-bit data transmission and the beginning of the next data to be sent. (4) The following 1-bit decides on whether the master will drive the data line or the slave will. If this bit is '1', the master will drive , but if '0' the slave will drive the data line. (5) The following 7-bit data is the register address of the specified slave device; the 7-bits for an address allows 128 register addresses for slaves. (6) The following high 1-BIT data is a dummy data. (7) The following 8-BIT data is the data in the device to be driven. (8) The following 1-BIT data is a dummy data, which marks the end of the 8-bit data transmission and beginning of the next data to be sent. (9) The following 1-bit decides on whether the master will drive the data line or the slave will. If this bit is '1', the master will drive , but if '0' the slave will drive the data line.
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TX IF/BBA WITH AGC
(10) The following 7-bit data is the register address of the specified slave device. (11) The following high 1-BIT data is a dummy data. (12) The following 8-BIT data is the data in the device to be driven. (Continuos data transmission such as this can be ended with a 1-byte transmission or can be read/written repeatedly.) (13) After the last data is sent, the data line opens and becomes high; (14) CLK continues for half the 1-clock cycle and then becomes high; (15) STB becomes high as soon as the clock becomes high and this marks the end of data transmission.
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TX IF/BBA WITH AGC
S1M8657
Modes of Operation S1M8657 can be controlled by parallel control mode or by SPI bus. The analog switch , an existing external component, in the IC an be also controlled through separate specified parallel inputs or by SPI. The modes of operation can be formed by parallel inputs such as FMB, IDLEB, and PAON, or by related SPI registers, as shown in Table 1. Table 1. Mode control in the parallel mode control MODE CDMA talk CDMA idle FM talk FM idle Tx puncture (SPI Only) FMB H H L L X IDLEB H L H L H PAON H X H X L
The modem in CDMA transmit mode operates the I and Q DAC in S1M8657, which then outputs the CDMA spread-spectrum with Tx IF mid-frequency. All the circuits in S1M8657 are stopped in CDMA receive mode (Idle). The modem only operates Q-DAC in the FM transmit mode (Talk). Besides this, all CDMA related circuits are stopped. The signal for FM modulation passes through the Q-FM-LPF (FM-MOD) output pin to come out. All circuits in S1M8657 are stopped in FM receive only mode (Idle). Because Tx puncture mode can only be controlled through the SPI bus, it turns on and off the blocks related to the intervals with no data. By doing so, it minimizes the consumption current. The SPI registers related to this feature are controlled by setting PAON = Low, SEN = High, IDLEB = High. Tx Phase Locked Loop S1M8657 has a built-in programmable PLL which can determine the IF mid-frequency. If the SPI BUS is not used, the default value in the built-in register must be used; the Tx IF frequency is 130.38Mhz when TCXO = 19.68Mhz. The block diagram of the PLL is shown in Figure 7. The PLL is composed of the VCO, R-Divider, NDivider, and Phase Detector, while the Loop filter and VCO components are outside S1M8657. The divide ratios in the PLL R and N counters can be programmed through the SPI bus. These can change the phase comparison frequency. The N-Counter is composed of a 9-BIT A-Counter and 4-BIT B-Counter and 8/9 or 16/17 DualModulus Prescaler.
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TX IF/BBA WITH AGC
to Mixer
PLLN0[7:4]
Divide by 2 N Counter
TX_VCO_T1 TX_VCO_T2
PLLN1[4:0]
PLL_MODE[4:3]
PDISET A-Counter Phase detector Prescaler P or P+1 B-Counter Charge pump Lock detector PDOUT
TX VCO
LOCK
TCXO
R-Counter
PLLR0[7:0] PLLR1[1:0] PLLN0[3:0] PLLR1[7:5] PLL_MODE[6]
Figure 7. Tx PLL Synthesizer Block Diagram
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TX IF/BBA WITH AGC
S1M8657
The A and B-Counter divide ratios can be changed by programming the PLLNO and PLLN1 among the SPI registers. They pass through the VCO internal output, TXVCO_OUT, and are input to the prescaler, and the prescaler outputs are input to A and B-counters. If the B-Counter is not "0", the Prescaler divides by P+1(division ratio of 9 or 17 ); if B-Counter is "0", the Prescaler divides by P(division ratio 8 or 16). If A-Counter becomes "0", N-Counter is reset. If A-Counter output becomes fv, this becomes the comparison input for the PD (phase comparator). R-Counter can be changed by programming PLLR0 and PLLR1 of the SPI registers. As a 10-bit divider, R-Counter divides TCXO, which is then used as the reference input for the PD.
MSB
LSB
PLLN0[3:0] 4-bit B-counter
PLLN1[4:0]
PLLN0[7:4]
9- bit A-counter
Figure 8. Map of N Counter
MSB
LSB
PLLR1[1:0]
PLLR0[7:0]
Figure 9. Map of R Counter The N-counter divide ratio (N) changes according to the prescaler value and is determined by the following equation. N = P x A + B, where A 512, 0 B (P-1), and B < A. The prescaler can use PLLN1[7] to select from either 8/9 or 16/17, the reference value being 16/17. If this bit becomes "0", 8/9 is chosen as the prescaler divide ratio. N-Counter, composed of the 9-BIT A-Counter and 4BIT B-Counter, lowers the VCO frequency and sends it to the PD. PLL equation : N-Counter divide ratio N = fVCO/fPD A-Counter divide ratio A = Int(N/P), A 512. The value of A written into PLLN1 and PLLN0 as shown in Figure 8 is a binary value for A-1. For example, the reference values, PLLN1[4:0]=00000 and PLLN0[7:4]=1100, are decimal, 12, and A is for 13. The B-counter can be programmed with PLLN0[3:0]. B = N - P x A, 0 B 15, P=16 The reference value for A and B-Counter (A=13, B=4) makes the VCO oscillating frequency equal to 260.76 MHz when TCXO is at 19.68MHz, and PD phase comparison frequency becomes 1.23MHz. The 10-bit R-counter can be programmed using the SPI registers, PLLR0 and PLLR1. The R-Counter makes the fR input signal for PD based on the TCXO reference signal. R-Counter divide ratio R = fREF/fPD The R-counter value set based on PLLR0 and PLLR1 is for R-1; for example, when PLLR0 = 00001111 and PLLR1=00, decimal value is 15, but it is R-1, real value R is 16.
19
S1M8657
TX IF/BBA WITH AGC
[Order of divide ratio calculation] VCO = 260.76MHz, TCXO = 19.68MHz, Phase detect frequency = 1.23MHz, Prescaler = 16 1) Determine the value of N : N = fVCO/fPD = 260.76MHz/1.23MHz = 212 2) Determine the value of A : A = Int(N/P) = Int(212/16) = 13 When this value is set in the register, the value of A-1(12) must be placed. Binary value is 000001100. 3) Determine the value of B : B = N - P x A = 121 - 16 x 13 = 4 4) Determine the value of R : R = fREF/fPD = 19.68MHz/1.23MHz = 16 The R register value is R-1 so 15 must be written. Binary value is 0000001111. The external PDISET resistance determines the charge pump from PDOUT. This resistance determines the current flowing between PDISET and GND as follows. Io = Rset/0.64V Io is the charge-pump current when the PLL is locked. If the resistance is 39k, Io becomes 16uA. The charge-pump current is classified into lock mode current and acquisition mode current to quickly stabilize the un-locked IC. The charge-pump current of the acquistion mode flows 10 times faster than that of the lock mode, thus providing faster stability. Although the Lock-Acquisition current can be changed from one to the other, the SPI PLL_Mode [4:3] register value can be used to permanently set the charge-pump current as either acquisition mode current or lock mode current. However, the type of current to be set should be carefully decided based on the amount of surrounding noise flowing into VCO. The charge-pump polarity can be change with PLLR1[4] to respond to the various conditions of the capacitor, whose value can be changed "+' or "-" for the varactor signal, according to how the VCO is used. A lock pin has been prepared to indicate that lock has occurred because the Tx frequency has entered the set band. This pin can be used to select from either the open-drain output or CMOS output. If the OPEN_DRAIN output is selected, an external 10k Pull up resistance is required. PLL_MODE[6] can be set to select the output type. Lock -unlock states can be determined by counting how many times the phase difference between the signal in the IC and the reference signal matches within the set phase difference band. Two criteria which can be used to detemine the lock are the phase difference band and the frequency of phase match during a set period. Here the user can select the frequency of phase match, the purpose of which is to determine whether or not the lock is a stable lock or a temporary lock condition. Namely, the lock condition ,when there are many phase matches, is a very stable condition, but it requires time. The phase difference here refers to the phase difference between the N-counter output fv and R-counter output fR. Whether or not to cancel the lock condition can be decided by determining how many times 2 phase differences fall within the set range within a specified duration. PLLR1[7:5] SPI register is used to set the phase match or unmatch frequency limit. Here , this limit is called the Lock-length, which is determined as follows: fR is the reference frequency in the phase comparator. fR = fTCXO/R, fTCXO is the basic TCXO frequency, R is the divide ratio for the basic TCXO frequency(R-Counter) fv is the VCO dividing frequency which is compared to the reference frequency in the phase comparator. fv = (fVCO + fERROR)/N, where fVCO is the VCO basic frequency and fERROR is the allowable maximum frequency range. Based on the above equation, the number of PD pulses required for the VCO frequency in a set band is NPD = 2 x TTCXO/(1/fR - 1/fV), TTCXO is the period of the TCXO basic frequency. The number of TCXO pulses for the VCO frequency in a set range is NTCXO = R x NPD where, Lock-length M = log2(NTCXO) - 13 Lock counter length is 2(M+13).
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S1M8657
The M in binary can be set by changing the PLLR1[7:5] register value. And normally, fERROR is designed to the limit of 1kHz. [An example of a Lock length design ] fVCO = 260.76MHz; fTCXO = 19.68MHz; fERROR = 1kHz; R = 16, N = 212 fR = fTCXO/R = 19.68MHz/16 = 1.23MHz fv = (fVCO + fERROR)/N = 1230004.71698 NPD = 2 x TTCXO/(1/fR - 1/fv) = 32600 NTCXO = R x NPD = 16 x 32600 = 521600 M = Roundup{log2(NTCXO)} - 13 = Roundup(18.9926) - 13 = 6 Therefore. Lock detector length is 219 TCXO. General Purpose ADC The GP-ADC for the system monitor has a built-in 3-input switch Serial 8-BIT A-D Converter and is used generally used to sense the temperature, and battery amount and type. The GP-ADC can be controlled by the following methods. Parallel control as in the existing S1M8653B when the SPI is not used and SEN = low. GPENA, GPDATA, and GPCLK must be used. Basic and enhanced modes exist with SPI use when SEN = High : Controlled through the SPI register and GPENA in the Basic Mode(TXMODE_CONT[0] = Low), and can output through either the SPI register or GPDATA and GPCLK pins. : Controlled according to the contents in the GPADC_MODE[7:0] in the Enhanced Mode(TXMODE_CONT[0] = High). General Purpose ADC Operation without SPI (SEN = low) When SEN = low, the Serial BUS(SPI BUS) is not used. In such a case, GP-ADC is controlled through SLSB, SMSB, GPENA, GPDATA and GPCLK provided from external pins or data must be sent. Under these conditions, the GP-ADC is reset at the rising edge of GPENA from the modem and starts the conversion. The converted digital code is synchronized to the continuous 9 GPCLK and sent to the modem. To start a new GPADC conversion, GPENA must be at Low. Input range or signal are selected based on the SMSB/PAON and SLSB/CLK states, as shown in Table 2. Table 2. Input and Range Select (SEN = low) SMSB 0 0 1 1 SLSB 0 1 0 1 GPIN GPIN1 GPIN1 GPIN2 GPIN3 Vin MID 0.75V 1.5V 1.5V 1.5V Input Range 0.5V 2V 2V 2V LSB/Step 2mV 8mV 8mV 8mV Zin
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S1M8657
TX IF/BBA WITH AGC
General Purpose ADC Enhanced-Mode Operation Using SPI (SEN = high, TXMODE_CONT[0] = high) When SEN = High the SPI BUS can be used. The GP-ADC operates in the basic mode or enhanced mode. If the TXMODE_CONT[0] is "1", it operates in the enhanced mode and the SPI registers control the input selection, clock frequency and input range. The basic setting is the Basic Mode. If TXMODE_CONT[0] = "1" in the basic mode, the GP-ADC operates in the enhanced mode. If all GP-ADC related controls and input/output function are conducted through the SPI bus, the GP-ADC only outputs the SPI input/output. GPENA can also drive GP-ADC; in this case, GPDATA and GPCLK are output and save at the same time in the SPI register, GPADC_RSLT[7:0], except that nothing can be input to the input select pins , SMSB/PAON and SLSB/CLK. It's simpler to think that in this mode the SPI registers perform the roles of what the parallel control pins did in the existing S1M8653B If GPENA and TXMODE_CONT[7] = High, GP-ADC starts the conversion. Moreover, for a new conversion, GPENA and TXMODE_CONT[7] must be left at Low, and restart begins at the rising edge of when they become high. While conversion is going on, GP-ADC cannot receive any signals. GPADC_RSLT[7:0], which has the GP-ADC conversion value, maintains its previous value until the end of the new conversion. Table 3. Enhanced-Mode Register Definition GP MODE GPADC_MODE[7:0] Default
CLOCK Divide Ratio
Input Range D5 0 D4 1 D3 0 D2 0
Input Select D1 0 D0 0
D7 1
D6 0
Table 4. Enhanced-Mode Analog MUX GPADC_MODE[1:0] 00 01 Input Select GPIN1 Reserved GPADC_MODE[1:0] 10 11 Input Select GPIN2 GPIN3
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S1M8657
Table 5. Enhanced-Mode Input Range Selection GPADCV[5:2] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Vin(Mid) 1.0V 2.0V 1.5V 1.5V 0.75V 1.5V 1.5V 1.5V 0.5V 1.0V 1.25V 1.5V 2.0V 1.5V 1.75V 2.0V Input Range 1V 1V 2V 2V 0.5V 2V 2V 2V 1V 2V 0.5V 1V 2V 0.5V 0.5V 0.5V LSB mV/Step 4 4 8 8 2 8 8 8 4 8 2 4 8 2 2 2 Zin
GP-ADC Enhanced Mode inputs are shown in Table 5. The IC input impedance is always kept high to reduce the loading effect of the input impedance. However, if the external input divider impedance is very large, the parasitic capacitor cannot charge or discharge quickly enough, generating a high speed conversion error. Therefore, it is best to use a low resistance at the input terminal. The LSB step is the difference between the input voltages that generate two codes, respectively. This is shown in Table 5. The GP-ADC needs the clock for conversion. This clock self-divides and uses TCXO and influences the conversion time. Although a 412kHz clock was used in S1M8653B, this IC can select from clock speeds between 308kHz - 1.23 MHz, as shown in Table 6, according to the contents in SPI register GPADC_MODE[6:7]. The recommended clock speed is between 410kHz - 615kHz. Table 6. GP-ADC Clock Divide Ratio GPADC_MODE[7:6] 00 01 10 11 Clock Divide Ratio 16 32 48 64 System Clock(TCXO = 19.68MHz) 1.23MHz 615kHz 410kHz 308kHz
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S1M8657
TX IF/BBA WITH AGC
General Purpose ADC Basic-Mode Operation Using SPI (SEN = high, TXMODE_CONT[0] = low) SPI can be used when SEN= high. The GP-ADC operates in the basic mode. Under these circumstances, GPADC is under the control of the SPI registers. The results of conversion can be output to not only the SPI register GPADC_RSLT[7:0] but also to GPDATA and GPCLK. When the basic mode turns on and SPI starts, they are automatically set. If the TXMODE_CONT[0] is "0" and all GP-ADC related controls and input/output function are conducted through the SPI bus, the GP-ADC only outputs the SPI input/output. GPENA can also drive GP-ADC; in this case, GPDATA and GPCLK are output and save at the same time in the SPI register, GPADC_RSLT[7:0]. In this mode, MODE_CONT[6:5] register holds the parallel input pins, SMSB/PAON and SLSB/CLK. If GPENA changes from low to high or GPDAC_MODE[7] register from "0" to "1", the GP-ADC stars the conversion. Essentially these indicate the start of conversion in basic mode. For a new conversion, these GPENA and GDAC_MODE[7] must be left at low state and intialization starts at the rising edge of when they become high. While conversion is going on, GP-ADC cannot receive any signals. GPADC_RSLT[7:0], which has the GP-ADC conversion value, maintains its previous value until the end of the new conversion. Table 7. GP-ADC Range Select in Basic Mode GPADC_MODE[4] 0 0 0 0 1 1 1 1 TXNODE_CONT[6:5] 00 01 10 11 00 01 10 11 Vin Mid 1.0 2.0 1.5 1.5 0.75 1.5 1.5 1.5 Input Range 1.0 1.0 2.0 2.0 0.5 2.0 2.0 2.0 LSB(mV) 4 4 8 8 2 8 8 8 GPADC Input GPIN1 GPIN1 GPIN2 GPIN3 GPIN1 GPIN1 GPIN2 GPIN3 Zin
GP-ADC can select from various input range as well as resolution value for each mid-voltage and LSB. It has a built-in input switch, which allows for easy connection with the input sensor. All programmable options are set by SPI registers TXMODE_CONT[6:5] and GOADC_MODE[4]. General Purpose ADC Conversion Time GP-ADC conversion time is determined based on the TCXO and GP-ADC clock divide ratio in the SPI register GPADC_MODE[7:6]. GP-ADC needs a total of 6 GPCLK cycles from its restart to start of data sampling; the required ADC conversion time is 8 and 1/2 GPCLK cycles. A total of 14.5 GPCLK cycles are used. Table 8. Maximum Conversion Time GPADC_MODE[7:6] TCXO frequency Divide ratio Conversion time us, max Units MHz 00 19.68 16 11.79 01 19.68 32 23.58 10 19.68 48 35.37 11 19.68 64 47.17
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TX IF/BBA WITH AGC
S1M8657
CONTROL REGISTERS
Register name RESET Address 0x00 R/W W Default vale Description Reset. Resets S1M8657 and all the register values are returned to their original value. SPI_ID. All slaves have an independent ID, which is used to distinguish the devices connected to the SPI bus and to send data to the desired device. PLLN0. Determines the divide ratio needed in the PLL divider. PLLN1. Determines the divide ratio needed in the PLL divider. PLLR0. Determines the divide ratio needed in the PLL divider. PLLR1. Determines the divide ratio needed in the PLL divider. PLL_MODE
SPI_ID
0x01
R
0x2A
PLLN0
0x02
R/W
0xC4
PLLN1
0x03
R/W
0x80
PLLR0
0x04
R/W
0x0F
PLLR1
0x05
R/W
0xD0
PLL_MODE not applied not applied not applied TXMODE_CTL GPADC_RESULT GPADC_MODE ON_OFF
0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0E
R/W not used not used not used R/W R R/W R/W
0x00
0x02 0x90 0x08
TXMODE_CTL Sets the transmission mode GPADC_RESULT GP-DATA storage. GPADC_MODE Sets the GP-ADC. ON_OFF Decides on whether to operate the functional block to be used in Tx puncture. To use this register, PAON must be low and Talk mode must be in place.
Reserved Reserved
0x10 0x11
Absolutely not used. Absolutely not used.
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S1M8657
TX IF/BBA WITH AGC
DESCRIPTION OF REGISTER
ADDRESS 00 01 02 NAME RESET SPI_ID PLLN0 [7:0] TYPE W R R/W BITS [5:0] [7:4] Description This is used like a command and if this address is accessed, all register values are restored to their original set value. This ID number must be used to use the registers as S1M8657 in this IC. SPI_ID = 2Ah PLLAC[3:0]. Default = 1100. Refers to the lower 4-bit in the 9-BIT A-Counter. Remember that the total 9-BIT value refers to the A-1 value. PLLBC[3:0]. Default = 0100. Register that sets the 4-BIT B-Counter. PSC_MODE, Default = 1. Sets the Prescaler Dual Mode. 1: P = 16 Mode, with divide ratio of 16 or 17. 0: P = 8 Mode, with divide ratio of 8 or 9. Default = 00 Absolutely not used. PLLAC[8:4]. Default = 00000. Refers to the upper 5-bit in the 9-BIT A-Counter. Remember that the total 9-BIT value refers to the A-1 value. PLLRC[7:0]. Default = 00001111. Refers to the lower 8-bit in the 10-BIT A-Counter. Remember that the total 10-BIT value refers to the A-1 value. LOCK_LEN. Default = 110. Lock output set register sets the lock output by detemining the time cut-line for level of PLL & VCO stabilization Phases must match duringTCXO*2(M+13) for lock. PD_MODE. Default = 1 Decides the polarity of the phase comparator gain (+ or -1). 0: Negative VCO gain (-Kv) 1: Normal operation. Default = 00, Absolutely not used. PLLRC[9:8]. Default = 00. Refers to the upper 2-bit in the 10-BIT R-Counter. Remember that the total 10-BIT value refers to the R-1 value. Default = 0. Absolutely not used. LOCK_MODE. Default = 0. Assigns the lock output form, the lock detector output. 1: Standard CMOS output 0: Requires an external pull up register because of the open drain output. Default = 0 Absolutely not used.
[3:0] 03 PLLN1 [7:0] R/W [7]
[6:5] [4:0]
04
PLLR0 [7:0]
R/W
[7:0]
05
PLLR1 [7:0]
R/W
[7:5]
[4]
[3:2] [1:0]
06
PLL_MODE
R/W
[7] [6]
[5]
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TX IF/BBA WITH AGC
S1M8657
DESCRIPTION OF REGISTER (Continued)
ADDRESS NAME TYPE BITS [4:3] Description CHG_PMP. Default = 00. Sets the Charge-pump Mode. 00: Normal operation( Separates the current amount for Lock- Aquisition Mode.) 01: not used 10: Always operates it with 10x Acquisition current. 11: Always operates it with 1x Lock current. Default = 000, Reserved GPADC_ON. Default = 0. GP-ADC conversion start command register. This bit must be on stand-by as "0" to start a new conversion. 1: Resets GPADC and starts conversion. 0: GPADC conversion stand-by. GP_SMSB. Default = 0 Upper 1-bit of the 2-bit input for selecting input switch. 1: SMSB is "1". 0: SMSB is "0". GP_SLSB. Default = 0 Lower 1-bit of the 2-bit input for selecting the input switch. 1: SLSB is "1". 0: SLSB is "0". CDMA_MODE. Default = 0(FM) Replaces the existing FMB pin function. 1: Sets CDMA Mode. 0: Sets FM Mode. IDLE_MODE. Default = 0(IDLE) Replaces the existing IDLEB pin function. 1: Talk Mode. 0: Idle Mode. Default = 0, Not used. Default = 1, Not used. GPENH. Default = 0 Select bit for enhanced mode or basic mode in the GP-ADC Mode 1: GPADC is set to Enhanced Mode. 0: GPADC is set to Basic Mode. Saves the most recent conversion value as read-only.
[2:0] 0A TXMODE_ CONT [7:0] R/W [7]
[6]
[5]
[4]
[3]
[2] [1] [0]
0B
GPADC_RSLT
R
[7:0]
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S1M8657
TX IF/BBA WITH AGC
DESCRIPTION OF REGISTER (Continued)
ADDRESS 0C NAME GPADC_MODE TYPE R/W BITS [7:6] Description GPADC_CLK. Default = 10. Sets the internal clock divide ratio for GP-ADC conversion. 00: TCXO/16, GPADC Clock=1.23MHz with TCXO=19.68MHz 01: TCXO/32, GPADC Clock=615kHz with TCXO=19.68MHz 10: TCXO/48, GPADC Clock=410kHz with TCXO=19.68MHz 11: TCXO/64, GPADC Clock=308kHz with TCXO=19.68MHz GPADC_RAN. Default = 0100 GP-ADC input range and precision selection. (TXMODE_CONT[0] = 0)
GPADCV[5:2] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Vin Mid 1.0 2.0 1.5 1.5 0.75 1.5 1.5 1.5 0.5 1.0 1.25 1.5 2.0 1.5 1.75 2.0 Input Range LSB Mv/Step 1 1 2 2 0.5 2 2 2 1 2 0.5 1 2 0.5 0.5 0.5 4 4 8 8 2 8 8 8 4 8 2 4 8 2 2 2 Zin
[5:2]
[1:0]
GPADC_IN. Default = 00. Selects one of the 3-inputs. 00: IN1, 01: not used, 10: IN2, 11: IN3
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TX IF/BBA WITH AGC
S1M8657
DESCRIPTION OF REGISTER(Continued)
ADDRESS 0E NAME TX_PWR TYPE R/W BITS [7] Description TXDAC_PWR. Default = 0 Stops the TX-DAC. 1: TXDAC stop. 0: TXDAC operation. TXFLT_PWR. Default = 0 Stops TX-CDMA/FM Filter. 1: TX filter stop. 0: TX filter operate. UPMIX_PWR. Default = 0 Stops TX-VCO, Mixer, and Quad_gen. *Advantageous in terms of set-up time when not used. 1: TX VCO, Mixer, and Quad_gen stop. 0: TX VCO, Mixer, and Quad_gen operate. TXAGC_PWR. Default = 0 Stops TX-AGC. 1: TXAGC stop. 0: TXAGC operate. TXPATH_PWR. Default = 1 Stops TX-AGC. 1: TXAGC stop. 0: TXAGC operate. TXPLL_PWR. Default = 0 Stops the PLL. *Do not use when there is a problem with set-up time. 1: TX_PLL stop. 0: TX_PLL operate. TXMIX_PWR. Default = 0 Stops TX-Mixer and Quad_gen. *Recommend using this bit rather than UPMIX_PWR bit. 1: TX Mixer and Quad_gen stop. 0: TX Mixer and Quad_gen operate. Not used.
This register is valid only when the PAON pin is at low.
[6]
[5]
[4]
[3]
[2]
[1]
[0]
When IDLEB = Low, minimum bias current is maintained by stopping all the TX circuit functions. To use the above Tx Puncture function, the external control pin PAON must be at low, and the IDLEB register bit must be at high. If PAON is High, it does not respond to the PX_PWR register contents.
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S1M8657
TX IF/BBA WITH AGC
GRAPH
-30 -40 -50
0 Rs=3.3K -20
Po ACPR2
75 65
Phase noise(dBc/Hz)
Output Power(dBm)
-60 -70 -80 -90 -100 -110 -120 10 100 1K 10K 100K 1M
-40 -60 -80 -100 0.0 0.5 1.0 1.5 Vcntl(V) 2.0
ACPR1
55 45 35 25
2.5
3.0
Frequency offset(Hz) GRPH 3-1 S1M8657X01 VCO Open Loop Phase Noise GRPH 3-1 S1M8657 VCO Open Loop Phase Noise
GRPH 3-2 S1M8657X01 Output Power, ACPR vs.ACPRPerformance GRPH 3-2 S1M8657 Output Power, Vcntl vs. Vcntl for CDMA full-scale input. Performance for CDMA full-scale Input
115
+1 Rs=3.3K/Po=-6dBm
Rs=3.3K/PDM=3.3V 105
Output Variation(dB)
SNR BAND-1(dBc/Hz)
-25 0 +25 +50 +75 +100
95 85 75 65 55
0
-1
-50
Temperture(C) GRPH 3-3 S1M8657X01 Output Variation vs. Temperature GRPH 3-3 S1M8657 Output Variation vs. Temperature for CDMA full-scale input.
45 -80
-70
-60
-50
-40
-30
-20
-10
0
Lower sideband Power(dBm)
GRPH 3-4 S1M8657 SNR BAND-1 BAND-1 vs. Lower GRPH 3-4 S1M8657X01 CDMACDMA SNR vs. Lower sideband Pout. sideband Pout.
for CDMA full-scale Input
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TX IF/BBA WITH AGC
S1M8657
115
115
110
110 105 100 SNR-1(dB) 95 90 85 80 -80 Rs=3.3K/PDM=3.3V
105 100
Rs=3.3K/PDM=3.3V
SNR-1(dB)
95 90 85 80 -80
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Output Power(dBm)
Output Power(dBm) GRPH 3-6GRPH 3-6 S1M8657 CDMA SNR1.98M to 44Mhz offset. S1M8657X01 CDMA SNR BAND-1, BAND-1, 1.98M to
GRPH 3-5 S1M8657 CDMA SNR BAND-1, 100K to GRPH 3-5 S1M8657X01 CDMA SNR BAND-1, 100K to 1.98Mhz offset. 1.98MHz offset
44MHz offset
31
S1M8657
TX IF/BBA WITH AGC
TEST CIRCUIT
10K 0.033uF 2.2uF 10K TLOCK SW_PDST 38 37 TPDSET TCXOIN 10K 36 1nF 35 1nF 34 SW_IDL 33 SW_FM 5 6 10nF 7 8 9 10nF 10 11 12 13 14 15 16 17 18 19 20 27 30 29 28 IN3 IN2 IN1 R=22K TPLL SW_GP GPIN VCC 32 SW_SEN 31 SW_MSB SW_LSB SPI_PORT 1nF 10K 10K 10K VCEN TPDO TFMOD 10nF 40 39 SW_PDO 39K 1.8K
1SV229 TVCO 47pF 1uF 10nF 4pF 1nF 47pF 41
3.3uH
3.3uH
0.5K
0.5K
10nF 48 47 46
10nF 45 44 43 SW_VCO 42
7pF 2.3nH
1:8
1 TIF_MON 2 1nF 3 4 1nF
CLK STB DATA
7pF 1K
VCOIN
S1M8657
10nF10nF 21 22 23 24
26 25 GPCLK GPDATA GPENA
TCLKB TCLK TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0
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TX IF/BBA WITH AGC
S1M8657
48BCC PKG OUTLINE
7.00 + 0.10 #37 #1
#1 INDEX LASER MARK
7.00 + 0.10
TOP VIEW
7.00 + 0.10
SIDE VIEW
#13 6.15 TYP 0.045 + 0.10 0.045 + 0.10
#1
#25
0.0853/40.040 Stan off
5.0 TYP
#13
0.045 + 0.10 0.045 + 0.10
0.80 MAX Total height
C0.2 0.40 + 0.10
6.15 TYP
0.50 TYP 0.30 + 0.10
BOTTOM VIEW
#37
#25
6.15 TYP
6.15 TYP
5.0 TYP
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S1M8657
TX IF/BBA WITH AGC
PKG DIMENSION
48LQFP PKG OUTLINE
9.00 + 0.30 0-8 7.00 + 0.20 0.127
+ 0.10 - 0.05
9.00 + 0.30
7.00 + 0.20
0.10 MAX
#48
#1 0.50
0.18
+ 0.10 - 0.05
0.05 MIN (0.75) 1.40 + 0.10 1.60 MAX
0.08 MAX
NOTE: Dimensions are in millimeters.
34
0.50 - 0.20

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